Time
Day 1: October 14, 2025
7:30 – 9:00
Registration & Breakfast
9:00 – 9:30
Opening Remarks – PAINE 2024 Awards
General Chair and Program Chair
Plenary Session I
Chair: Nathan Edwards – Rapid Innovation & Security Experts Inc.
9:30 – 10:00
Keynote Talk I: Bridging Virtual and Physical: Accelerating U.S. Semiconductor Innovation with Digital Twin Technologies
Christopher Ritter – SMART USA Institute
10:00 – 10:30
Break
SESSION I: Invited Talks
Chair: Dr. Jennifer Schloss – MIT Lincoln Lab
10:30 – 10:50
Metrology Challenges & Solutions for Hybrid Bonding
Dr. Bongsub Lee – ADEIA
10:50 – 11:10
The Evolution of Electronics Packaging to Chiplet Architecture
Dr. Charles Woychik – Nhanced Semiconductors, Inc.
11:10 – 11:30
Enhancing Supply Chain Trust and Assurance with Artificial Intelligence
Dr. Matthew Areno – Midwest Microelectronics Consortium
11:30 – 11:50
FSE Assurance and 3-D Advanced HI Packaging Failure Analysis Lab
Matt Walsh – Florida Semiconductor ENGINE
11:50 – 1:00
Lunch
Plenary Session II
Chair: Dr. Tony Melaragno – US Naval Academy
1:00 – 1:30
Keynote Talk II: National Advanced Packaging Manufacturing Program
Dr. Rob Aitkens – CHIPS R&D Office
1:30 – 1:50
Visionary 1: Navigating the Post-Generative AI Era of Failure Analysis
Dr. Joy Liao – Nvidia
SESSION II: Special Session SEMI
Chair: Anshu Bahadur
1:50 – 3:20
Virtual Metrology
Dr. Anis Rahman – Applied Research & Photonics, Inc.
Dr. Min Gao – EMD Electronics
Steve Cho – Gauss Labs
Dr. Surya Kalidindi – Multiscale Technologies
3:20 – 3:50
Break
SESSION III: Paper Presentations
Chair: Emily Haines – Battelle
3:50 – 4:10
Toward In-House 3D Nanoscale X-ray Tomography of Integrated Circuits for Quality Control and Hardware Security at Speed of Need
Jordan Fonseca – National Institute of Standards and Technology
4:10 – 4:30
Lurking in the Shadows: Challenges for X-Ray Inspection to Uncover Electromigration-Based Hardware Trojans in Advanced Packaging
Katayoon Yahyaei – University of Florida
4:30 – 4:50
X-Ray Fault Injection Localization with a Shield on Powered and Unpowered Devices
Paul Grandamme – Université Jean Monnet-France
4:50 – 5:10
Metaheuristic Color Scheme Strategies for Enhanced Visual Inspection of 3D IC Layouts
Zhansen Shi – National University of Singapore
5:10 – 5:30
Magnetic Field Imaging using Diamond Nitrogen-Vacancy Centers for Fault Detection and Security of Semiconductor and Superconductor Electronics
Jennifer Schloss – MIT Lincoln Laboratory
5:30 – 6:30
Exhibit and Poster Session
6:30 – 8:00
Social Event
Time
Day 2: October 15, 2025
7:00 – 8:30
Breakfast
Plenary Session III
Chair: Dr. Adam Waite – Battelle
8:30 – 9:00
Keynote Talk III: Microelectronics Commons
Dr. Tim Morgan – Microelectronics Commons
9:00 – 9:30
Keynote Talk IV: Next-Generation Microelectronics Manufacturing
Saverio Fazzari – Booz Allen Hamilton
9:30 – 9:50
Break
SESSION IV: Special Session NIST
Chair: Dr. Nelson Hastings – NIST
9:50 – 10:50
Title: Insights into NIST Hardware Security Research Activities
Abstract: This session will provide insight into the hardware security research activities within NIST’s Information Technology Laboratory (ITL) and Communications Technology Laboratory (CTL). An overview of ITL’s hardware security activities will be presented including motivation, areas of research, and upcoming events; followed by a closer look at current research activities related to Side Channel Analysis (SCA).
Dr. Nelson Hastings, Dr. Jim Booth, Dr. Guru Venkataramani
10:50 – 11:10
Break
SESSION V: Invited Talks
Chair: Dr. Eric Cotts – Binghamton University
11:10 – 11:30
Hardware security vulnerabilities: Lessons learnt after nearly 800+bugs
Dr. Jeyavijayan “JV” Rajendran – Texas A&M University
11:30 – 11:50
Adventures in Hyperspectral Computed Tomography for Non-destructive Hardware Evaluation
Dr. Eric Goodman – Sandia National Laboratories
11:50 – 12:10
Electron Beam Assisted Back-Contact Free Electrical Atomic Force Microscopy
Dr. Umberto Celano – Arizona State University
12:10 – 12:30
Defect Imaging of Emerging Memory Materials via Electro-Optical Characterization
Dr. Thomas Beechem – Purdue University
12:30 – 2:00
Lunch
Plenary Session IV
Chair: David Torres – Red Ballon Security
2:00 – 2:20
Visionary 2: Keeping up with Moore’s Law: Silicon Reliability and Product Qualification challenges due to Technology Scaling
Amit Marathe – Google
SESSION VI: Panel Discussion
Moderators: Saverio Fazzari – Booz Allen Hamilton
2:20 – 3:30
The Role of AI in Redefining Physical Assurance
Dr. Adam Kimura – Battelle
Dr. Sarah Paluskiewicz – Northrop Grumman
Dr. Navid Asadi – University of Florida
Dr. Julian Warchall – IBM Research
Dr. Edward Jimenez – Sandia National Laboratories
3:30 – 4:00
Break
SESSION VII: Paper Presentations
Chair: Daniel Homiak – Lockheed Martin
4:00 – 4:20
Advancing Microelectronics Evidence-Based Assurance while Preserving Confidentiality: Copia
Nikhil Shenoy – Colvin Run Networks, Inc.
Nathan Edwards – Rapid Innovation and Security Experts, Inc.
4:20 – 4:40
Analysis of Temperature Effect on SRAM PUF For Low Cost Applications
Sayan Samanta – The University of Alabama in Huntsville
4:40 – 5:00
A Quantitative Means for Assessing Failure in SnBi-Based Solder Joints During Current Stressing
Eric Cotts – SUNY Binghamton
5:00 – 5:20
Post-Silicon Functional Verification and Validation: Chip to RTL Analysis
Tim McDonley – Battelle Memorial Institute
5:20 – 5:40
Evaluating multimodal foundation models for few-shot PCB identification and reasoning
Zachary Burns – Leidos Innovations Center
Time
Day 3: October 16, 2025
7:00 – 8:00
Breakfast
Plenary Session V
Chair: Dr. Pauli Kehayias – Sandia National Laboratory
8:00 – 8:30
Keynote Talk V: Secure Design-for-Test and Inspection Techniques for Trusted 3DIC
Antonio De la Serna – Siemens EDA
8:30 – 8:50
Hardware-Enabled Mechanisms for Verifying Responsible AI Development
Will Hodgkins – Center for AI Safety
8:50 – 9:10
Break
SESSION VIII: Invited Talks
Chair: Nikhil Shenoy – Colvin Run Networks
9:10 – 9:30
METIS Dissemination Portal for CHIPS Metrology Digital Data Products
Dr. June Lau – NIST
9:30 – 9:50
Mathematical Approaches to Microelectronics Assurance
Dr. Whitney Batchelor – Graf Research
9:50 – 10:10
Deep-Learning Side-Channel Analysis
Dr. Boyang Wang – University of Cincinnati
10:10 – 10:30
Chiplets and Reliability
Dr. Jason Rupe – Cablelabs
10:30 – 10:50
Break
SESSION IX: Paper Presentations
Chair: Dr. Sneha Sudhakaran – Florida Institute of Technology
10:50 – 11:10
Exploiting Electron-Beam Probing for Information Leakage in Advanced-Node Integrated Circuits
M Shafkat M Khan – Thermo Fisher Scientific Inc.
11:10 – 11:30
Converged Standardization: Improving Template Attack Success Using Aggregated Power Trace Self-Referencing
Dave Ingalls – Indiana University
11:30 – 11:50
Efficient Side-channel Leakage Assessment Using Deep Learning-based Feature Extractor and ANOVA
Yuta Fukuda – National Institute of Advanced Industrial Science and Technology – Japan
11:50 – 12:10
Enabling Algorithm Detection in the Presence of Interrupts: Using HAL for Side-Channel Interrupt Detection and Mitigation
Kevin Pintong – Binghamton University
12:10 – 1:10
Lunch
SESSION X: Paper Presentations
Chair: Dr. Akshay Kulkarni – Prairie View A&M University
1:10 – 1:30
Analyzing Sources of Fingerprints in Wireless Modules Using Microwave Measurements
Vishnuvardhan Iyer – National Institute of Standards and Technology
1:30 – 1:50
Multi-Granular Information Flow Tracking in RISC-V based SoCs
Dhruvakumar Aklekar – University of North Carolina at Charlotte
1:50 – 2:10
AuthenTree: A Scalable MPC-Based Distributed Trust Architecture for Chiplet-based Heterogeneous Systems
Ishraq Tashdid – University of Central Florida
2:10 – 2:30
FirmEM: Firmware Flashing Detection via Unintentional Electromagnetic Emissions
Elvan Ugurlu – Aether Argus Inc.
2:30 – 2:50
Break
SESSION XI: Paper Presentations
Chair: Dr. Rayhane Ghane – Ficontec
2:50 – 3:10
A Defense Electronics Supply Chain Root Cause Analysis-based Model to identify data features that are viable for counterfeit predictive analytics
Konstantinos Belesis – George Washington University
3:10 – 3:30
An AI-Empowered Multidisciplinary Approach to the Detection of Social Engineering Attacks
Anthony Melaragno – United States Naval Academy
3:30 – 3:50
Integrated-Circuit Supply Chain Verification Using Mask Set Comparison in the Open Source Context
Olivier Thomas – Texplained – France
3:50 – 4:10
Power Spectrum Analysis-Based Counterfeit Screening: A Hardware Comparison
Devon Richman – University of Maryland
4:10 – 4:30